Specifications, Features, Applications
Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from to 20V Undervoltage lockout for both channels CMOS Schmitt-triggered inputs with pull-down Matched propagation delay for both channels Internally set deadtime High side output in phase with input
VOFFSET IO+/VOUT ton/off (typ.) Deadtime (typ.) 600V max. 650 ns
The is a high voltage, high speed power MOSFET and IGBT driver with dependent high and low side referenced output channels designed for half-bridge applications. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic input is compatible with standard CMOS outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Internal deadtime is provided to avoid shoot-through in the output half-bridge. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates to 600 volts.
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in figures 7 through 10.
High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Allowable offset supply voltage transient (figure 2) Package power dissipation TA +25°C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8 Lead PDIP) (8 lead SOIC) (8 lead PDIP) (8 lead SOIC)
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side and logic fixed supply voltage Low side output voltage Logic input voltage Ambient temperature
Note 1: Logic operational for to +600V. Logic state held for -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details).
VBIAS (VCC, VBS) 1000 pF and = 25°C unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in figure 3.
Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Deadtime, LS turn-off to HS turn-on & HS turn-off to LS turn-on Delay matching, & LS turn-on/off
Min. Typ. Max. Units Test Conditions
VBIAS (VCC, VBS) = 15V and = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
VOH VOL ILK IQBS IQCC IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO-
High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic "1" input bias current Logic "0" input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current Output low short circuit pulsed current