dsPIC30F4013-30I/P

Description

dsPIC30F4013-30I/P

High-Performance Modified RISC CPU:

• • Modified Harvard architecture
  • C compiler optimized instruction set architecture
  • 84 base instructions with flexible addressing modes
  • 24-bit wide instructions, 16-bit wide data path
  • 16 x 16-bit working register array
  • Up to 30 MIPs operation:
    • DC to 40 MHz external clock input
    • Internal FRC input with PLL active (4x, 8x, 16x)
    • 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)
    • 10 MHz – 20 MHz oscillator input in HS/2 or HS/3 with PLL active (4x, 8x, 16x)
  • Peripheral and External interrupt sources
  • 8 user selectable priority levels for each interrupt
  • 4 processor exceptions and software traps
  • Primary and Alternate interrupt Vector Tables

for more info please refer to complete Datasheet